1. Field of the Invention
The present invention is directed to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method and computer program for placing fill wires in an integrated circuit design.
2. Description of Related Art
In recent semiconductor manufacturing technology, copper wires or traces are typically used to conduct signals within each net in an integrated circuit die. As the net density increases, process restrictions are imposed on the metal to oxide ratio and the uniformity of distribution of the copper metal on the surface of the die. These process restrictions are a consequence of forming the metal traces on the die. The metal traces are made by cutting trenches into a surface oxide layer of the die, filling the trenches and the die surface with copper metal, and polishing the surface of the die to just below the top of the trenches. The copper-filled trenches constitute the traces that interconnect the cells of each net.
The rate of material removal during the polishing process is dependent on the metal density, that is, the ratio of copper to oxide on the surface of the die. If the metal density is not uniform across the die, then the traces will be thinner in the high density areas than in the low density areas. The varying trace thickness presents problems in net timing modeling and may result in performance failures in the manufactured die. To maintain a uniform trench height and corresponding trace thickness, the distribution of copper metal across the surface of the die must be kept uniform within a controlled tolerance.